A communication system between a memory controller and a memory employs chiefly a plurality of transmission lines (buses) and, usually, employs a shared bus system which enables three or more units to carry out the communication using physically the same transmission line. The shared bus features a large quantity of data transmitted and received per a unit time since a plurality of data are communicated in one cycle. Besides, only one bus may be used irrespective of the number of units, which makes it easy to vary the quantity of memory and to add (extend) the memory depending upon the system. As the shared bus, there can be exemplified JEDEC Standard 79, Double Data Rate (DDR) SDRAM Specification (document 1).
The scaling of the metal oxide film semiconductor transistor (MOS: metal oxide semiconductor) has contributed to strikingly increasing the processing ability of an integrated circuit (IC) and, particularly, of a central processing unit (CPU). In recent years, however, there remains a problem in that the processing ability of the computer system as a whole is not improved despite of an increase in the processing ability of the CPU. One of the causes may be that the speed of the main memory is slowing down relative to the processing ability of the CPU.
In particular, the interface between the memory controller and the memory employs the shared bus as described above accompanied by a problem of deviation (skew) in the timing among the data lines as the communication speed increases. Further, a number of units existing on the same line are accompanied by such problems as a difference in the timing among the units, a change in the transmission conditions depending upon the units and reflection of signals at points to where the units are connected. In the interface among the memories in high-speed memory controllers, therefore, it becomes necessary to use expensive registered DIMMs (dual inline memory modules) imposing imitation on the number of the memories that are connected, arousing problems such as an occurrence of error if all memory slots are used.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of transmitting data at high speeds, a data processing system and a memory system.
Another object of the present invention is to provide a semiconductor integrated circuit device capable of transmitting data at high speeds despite of its simple constitution, a data processing system and a memory system.
The above and other objects of the present invention as well as novel features of the present invention will become obvious from the description of the specification of the application and the accompanying drawings.